Analog-to-Digital conversion (A-D conversion) is required whenever real world signals that are analog are to be processed and analyzed by a computer. Multi-channel A-D conversions are required in many industrial, medical and measurement applications. Low power consumption is required on systems which involve, a large number of channels, and the upper limit for these systems may be a few milliwatts. In addition, for battery-operated systems, a low power A-D conversion is required for longer battery life.
FIG. 1 shows an example application of an Analog-to-Digital Converter (ADC). The input to the ADC is an analog shaped pulse. The ADC digitizes this pulse and provides a 12-bit digital output. The minimum sampling rate of an ADC is set by the bandwidth of an input signal. Following Nyquist criteria, the minimum sampling rate of the ADC should be twice the maximum frequency of the input signal. For applications such as radiation detection systems, the frequency of the events and the pulse width at the output of the filter (shaper) define the sampling rate. The shaper output has typically a peaking time of a fraction of microseconds. This implies that a sampling rate of a few Megasamples per second (Msps) is typically needed for these applications.
ADC resolution is another important parameter which defines the minimum change in the analog input that can be discriminated by the ADC. For a moderate-high resolution, 10 to 12 bit ADCs are typically required. Finally, the requirement on the clock, e.g., lowest possible clock frequency, and the available chip area are other factors contributing to the selection of the ADC topology.
It is preferred to have a low power 12-bit ADC for supporting multi-channel applications. It is also preferred to have an ADC that has the capability of supporting a sampling rate of a few Msps with minimum requirement on the clock and while occupying a relatively small area.
A few topologies of ADCs can be found in the literature that approach these specifications. For moderate-high resolution and the sampling rate of a few Msps, these architectures include Pipeline and Successive Approximation Register.
The Successive Approximation Register (SAR) ADC consists of a comparator, a Digital-to-Analog Converter (DAC) and a register. An input signal is successively compared to the voltage generated by the DAC and each bit in the register is set to ‘1’ or ‘0’ depending on the result of the comparison. A disadvantage of the SAR ADC is that for a N bit resolution, it requires N clock cycles and hence a fast clock. Additionally, the SAR ADC requires the DAC and the comparator to be 12-bit accurate, which implies higher power consumption. A SAR ADC is described in Davidovic, M.; Zach, G.; Zimmermann, H.; “A 12-bit fully differential 2 MS/s successive approximation analog-to-digital converter with reduced power consumption,” Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010 IEEE 13th International Symposium, pp. 399-402, 14-16 Apr. 2010, which meets the requirement of 12-bit and 2 Msps, but has a relatively high power consumption of 10 mW and an area of 1.1 mm2, and which is incorporated by reference in its entirety as if fully set forth in this specification.
Charge redistribution SAR ADC is another candidate that may match the required specifications. However, this topology of ADC requires large capacitors. The linearity of the ADC depends on the matching between the capacitors. A charge redistribution SAR ADC is described in Otfinowski, P., “A 2.5 MS/s 225 p.W 8-bit charge redistribution SAR ADC for multichannel applications,” Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference, pp. 182-185, 24-26 Jun. 2010, which is incorporated by reference in its entirety as if fully set forth in this specification. But the redistribution SAR ADC has a resolution limited to 8 bits.
The pipeline ADC consists of a lower resolution DAC and ADC and multiple stages of flash ADCs. A major drawback of pipeline ADCs is the power consumption. A pipeline ADC is described in Rarbi, Fatah; Dzahini, Daniel; Gallin-Martel, Laurent, “A low power 12-bit and 25-MS/s pipelined ADC for the ILC/ECAL integrated readout,” Nuclear Science Symposium Conference Record, 2008. NSS '08. IEEE, pp. 1506-1511, 19-25 Oct. 2008, which supports a high sampling rate, but has a high power consumption of 42 mW, and which is incorporated by reference in its entirety as if fully set forth in this specification. Some of the more recent ADCs are included in Table 1 below along with their sampling rates and power consumption.
Figures of Merit (FOM) are frequently used to compare the performance of ADCs. A typical FOM is given in Walden, R. H., “Analog-to-digital converter survey and analysis,” Selected Areas in Communications, IEEE Journal of Selected Areas Communications, vol. 17, no. 4, pp. 539-550, April 1999, which is incorporated by reference in its entirety as if fully set forth in this specification, and in which the FOM is represented by:FOM=2b*fs/Pdiss 
where, b is the resolution, fs, is the sampling frequency and Pdiss is the power dissipated. Table 1 compares a few ADCs from recent years with respect to resolution, power, sampling rate, area and FOM. The Pipeline ADC listed in the first row of Table 1 was described in Peach, C. T.; Un-Ku Moon; Alistot, D. J., “An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 μm CMOS,” Solid-State Circuits, IEEE Journal of Solid State Circuits, vol. 45, no. 2, pp. 391-400, February 2010, which is incorporated by reference in its entirety as if fully set forth in this specification.
The Logarithmic Pipeline ADC listed in the second row of Table 1 was described in Jongwoo Lee; Kang, J.; Sunghyun Park; Jae-sun Seo; Anders, J.; Guilherme, J.; Flynn, M. P., “A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC,” Solid-State Circuits, IEEE Journal of Solid State Circuits, vol. 44, no. 10, pp. 2755-2′765, October 2009, which is incorporated by reference in its entirety as if fully set forth in this specification.
The Charge Redistribution SAR ADC in Table 1 was described in van Elzakker, M.; van Tuijl, E.; Geraedts, P.; Schinkel, D.; Klumperink, E.; Nauta, B., “A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s,” Solid-State Circuits, IEEE Journal of Solid State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010, which is incorporated by reference in its entirety as if fully set forth in this specification.
The Two Step ADC in the fourth row of Table 1 was described in Yung-Hui Chung; Jieh-Tsorng Wu, “A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC,” Solid-State Circuits, IEEE Journal of Solid State Circuits, vol. 45, no. 11, pp. 2217-2226, November 2010, which is incorporated by reference in its entirety as if fully set forth in this specification.
The Algorithmic ADC in the fifth row of Table 1 was described in Min Gyu Kim; Hanumolu, P. K.; Un-Ku Moon, “A 10 MS/s 11-bit 0.19 mm2 Algorithmic ADC With Improved Clocking Scheme,” Solid-State Circuits, IEEE Journal of Solid State Circuits, vol. 44, no. 9, pp. 2348-2355, September 2009, which is incorporated by reference in its entirety as if fully set forth in this specification.
The Zero-Crossing based Pipeline ADC in row 6 of Table 1 was described in Brooks, L.; Hae-Seung Lee, “A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC,” Solid-State Circuits, IEEE Journal of Solid State Circuits, vol. 44, no. 12, pp. 3329-3343, December 2009, which is incorporated by reference in its entirety as if fully set forth in this specification.
The SAR ADC in Table 1 was described in Chun-Cheng Liu; Soon-Jyh Chang; Guan-Ying Huang; Ying-Zu Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” Solid-State Circuits, IEEE Journal of Solid State Circuits, vol. 45, no. 4, pp. 731-740, April 2010, which is incorporated by reference in its entirety as if fully set forth in this specification.
The Pipeline ADC in row 8 of Table 1 was described in Andersen, T. N.; Hernes, B.; Briskemyr, A.; Telsto, F.; Bjornsen, J.; Bonnerud, T. E.; Moldsvor, O., “A cost-efficient high-speed 12-bit pipeline ADC in 0.18-vm digital CMOS,” Solid-State Circuits, IEEE Journal of Solid-State Circuits, vol. 40, no. 7, pp. 1506-1513, July 2005, which is incorporated by reference in its entirety as if fully set forth in this specification.
The Algorithmic ADC in row 9 of Table 1 was described in Esperanca, B.; Goes, J.; Tavares, R.; Galhardo, A.; Paulino, N.; Silva, M. M., “Power-and-area efficient 14-bit 1.5 MSample/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC,” Circuits and Systems, 2008. 1SCAS 2008. IEEE International Symposium, pp. 220-223, 18-21 May 2008, which is incorporated by reference in its entirety as if fully set forth in this specification.
It can be seen from Table 1 that most of the ADCs do not achieve the required resolution when the Effective Number Of Bits (ENOB) is measured. ENOB of the ADC is calculated from the Signal to Noise Ratio (SNR). The higher the SNR, the higher the ENOB. Accordingly, if a higher resolution is needed, more power will be consumed. In addition, architectures like the SAR ADC require a high speed clock that is dictated by the sampling frequency and the resolution.
TABLE 1SampResRatePowerAreaClockTechNumberArchitecture(bits)ENOB(Msps)(mW)(mm2)(MHz)FOM(nm)1Pipeline108.944211.11.2~423.87e121802Logarithmic85.62222.50.56~222.25e12180Pipeline3Charge108.7510.00190.025~105.38e1465RedistributionSAR4Two Step109.3410060.36~2001.70e13905Algorithmic11910150.19~1001.36e121306Zero-Crossing1210504.50.3~504.50e1390based Pipeline7SAR ADC109.18500.8260.0517~5006.19e131308Pipeline12102100.86~28.19e111809Algorithmic14121.54100.36~102.54e12130
U.S. Pat. No. 7,187,316 to Gianluigi De Geronimo, which is incorporated by reference in its entirety as if fully set forth in this specification, discloses an ADC that provides peak detection and A-D conversion of shaped analog pulses caused by an ionizing event in a radiation detection system without requiring a clock signal and using very little power. The A-D conversion occurs during a rising edge of a shaped pulse and conversion is complete when the peak occurs. However, the ADC in this U.S. patent is unable to provide a 12-bit resolution at the given speed.
In view of these and other considerations, there is a need to develop an analog-to-digital converter that is capable of meeting the requirements of lower power dissipation, smaller area, sampling rate capability of a few Msps, a 12-bit resolution, and lower requirement on the clock.